1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device which is equipped with a capacitor portion, and in particular, to a method of fabricating a semiconductor device, such as a semiconductor integrated circuit or the like, which is equipped with a capacitor portion.
2. Description of the Related Art
In semiconductor devices, and in analog circuits and RF (radio frequency) circuits in particular, a capacitor portion is an indispensable element. Conventionally, semiconductor devices, such as semiconductor integrated circuits, equipped with a capacitor portion have been structured as follows.
As illustrated in FIG. 8, underlayer wiring patterns 101A, 101B are formed on a semiconductor substrate 100. An insulating film layer 103 is formed on the underlayer wiring patterns 101A, 101B. At the insulating film layer 103 are formed a lower electrode 105, which is one electrode of a capacitor portion, and vias 104A, 104B for connecting a wire 107B for leading an electrode and the like. The lower electrode 105 is provided above (i.e., at the upper side of in FIG. 8) the vias 104A. The lower electrode 105 is connected to the vias 104A and the underlayer wiring pattern 101A, and to the wire 107B for leading an electrode via the via 104B. Moreover, a capacitor insulating film pattern 106 is formed so as to cover the lower electrode 105. An upper electrode 108 is provided on the capacitor insulating film pattern 106.
Such a conventional semiconductor device equipped with a capacitor portion is fabricated as follows.
First, an underlayer wiring layer is formed on the semiconductor substrate 100. The underlayer wiring patterns 108, 101B are formed by photolithography and etching processing. Next, the insulating film layer 103 is deposited on the underlayer wiring patterns 101A, to 101B. Thereafter, openings are formed in the insulating film layer 103. Tungsten or the like is filled into these openings so as to form the vias 104A, 104B.
Next, a metal layer is deposited. This metal layer is worked into a desired pattern by photolithography and etching processing, so as to form the lower electrode 105. Then, a capacitor insulating film layer is deposited, and is worked by photolithography and etching processing so as to form the capacitor insulating film pattern 106 to cover the lower electrode 105. At this time, the via 104B is exposed. Finally, a predetermined metal layer is layered thereon, and is worked by photolithography and etching processing so as to form the upper electrode 108 and the wirings 107A, 107B for leading an electrode.
Moreover, the semiconductor device equipped with a capacitor portion which is illustrated in FIG. 9 is known. The lower electrode 105, which is one electrode of a capacitor portion, is formed on the semiconductor substrate 100. The insulating film layer 103 is formed at both end portions of the lower electrode 105. The capacitor insulating film pattern 106 is formed on the insulating film layer 103 so as to cover the lower electrode 105 and the insulating film layer 103. Further, the upper electrode 108 is formed on the capacitor insulating film pattern 106 so as to cover the entire capacitor insulating film layer 106.
The semiconductor device equipped with a capacitor portion which is illustrated in FIG. 10H is also known. A metal layer 109, which becomes the lower electrode 105, is formed on the substrate 100 (see FIG. 10A). A resist pattern 102 is formed on the metal layer 109 (see FIG. 10B). The metal layer 109 is etched by using the resist pattern 102 as a mask, such that the lower electrode 105 is formed. The metal layer 109 which is to become the lower electrode 105 has a structure in which are layered a 100 nm Ti/TiN film (serving as a barrier metal) as the lowermost layer, and next, a 500 nm Alxe2x80x94Sixe2x80x94Cu (Si 3%, Cu 1%) film, and a 100 nm Ti/TiN film (for the purpose of preventing reflection) as the uppermost layer.
Thereon, a 100 nm CVD oxide film which is to become the capacitor insulating film pattern 106 is layered. A 100 nm Ti/TiN film, which serves as a metal layer 109B which is to become the upper electrode 108, is layered on the capacitor insulating film pattern 106 (see FIG. 10D). Then, the resist pattern 102 is formed thereon (see FIG. 10E). The metal layer 109B is etched by using the resist pattern 102 as a mask, so as to form the upper electrode 108 (see FIG. 10F).
Thereafter, an insulating film layer 110 serving as an inter-layer insulating layer is formed on the entire wafer surface. Planarizing (flattening) by CMP (chemical mechanical polishing) is carried out (see FIG. 10G), and an inter-layer film cap insulating film 111 is formed. The vias 104 are formed by photolithography and etching processing, and thereon, a metal layer 113 which supports the upper electrode is layered.
However, in the conventional methods for fabricating a semiconductor device equipped with a capacitor portion, the formation of the pattern of the lower electrode 105 by photolithography and etching processing, and the formation of the pattern of the capacitor insulating film 106 by photolithography and etching processing, are carried out independent of one another. Thus, there are drawbacks in that there are many processing steps, work is complicated, and costs increase.
Further, the capacitor insulating film pattern 106 which covers the end portions of the lower electrode 105 deteriorates (portion A in FIG. 8 and portion C in FIG. 9), and an electric field concentrates at a portion of the upper electrode 108 such that the breakdown voltage of the capacitor insulating film pattern 106 deteriorates (portion A in FIG. 8). In addition, due to the effect of the step formed by the underlayer wiring pattern 101A, the lower electrode 105 cannot be planarized well even if CMP is carried out, and there is the possibility that weak spots may arise in the capacitor insulating film pattern. Moreover, when the vias 104A are formed, a step is formed, and as a result, the flatness of the lower electrode 105 deteriorates, such that weak spots arise in the capacitor insulating film pattern. Due to this deterioration of properties, deterioration in breakdown voltage, and generation of weak spots, it is difficult for the capacitor insulating film pattern 106 to be made thin. A problem arises in that the capacity per unit surface area cannot be made large, which impedes the ability to make the semiconductor device more highly integrated.
Moreover, after formation of the lower electrode 105 and the capacitor insulating film pattern 106, the upper electrode 108 and the like are formed. Thus, at the stepped portions (portion B in FIG. 8, portion C in FIG. 9, and portion D in FIGS. 10F through 10H) of the end portions of the capacitor insulating film pattern 106, it is easy for metal wire remains 120 (see FIG. 10) at the time of etching processing to be generated. Problems arise such as these remains are a cause of short circuits occurring between adjacent patterns such that the reliability deteriorates.
The present invention was formed in order to overcome the above-described problems, and objects of the present invention are to provide a semiconductor device in which it is difficult for metal wire remains to be generated and in which reliability is improved, and to prevent a deterioration in breakdown voltage of a capacitor portion and aim for an increase in integration of semiconductor elements, and to decrease the number of fabrication processes so as to reduce costs.
In order to achieve the above object, a first aspect of the present invention is a method of fabricating a semiconductor device equipped with a capacitor portion, the method comprising the steps of: successively layering, on a substrate, a first metal layer which becomes a lower electrode and a wiring pattern, an insulating film layer, and a second metal layer which becomes an upper electrode; forming the upper electrode by subjecting the second metal layer to etching processing by using a resist pattern; forming a resist pattern for forming the lower electrode and the wiring pattern, at a region which covers the upper electrode; and etching the insulating film layer and the first metal layer in accordance with the resist pattern.
In accordance with the first aspect, first, the upper electrode is formed, and thereafter, the lower electrode is formed. Thus, no steps are formed at the first metal layer and the second metal layer. For example, no remains of metal wirings are generated at step portions at the time etching processing is carried out, and reliability can be improved.
Further, the upper electrode and the lower electrode are worked in that order. The lower electrode has a region which is wider than that of the upper electrode. Thus, the upper electrode is encompassed by the lower electrode, and there are no portions at the upper electrode which jut out beyond the lower electrode. Accordingly, the insulating film pattern is only the planarized portion directly beneath the upper electrode. Because a uniform electric field is applied, deterioration of breakdown voltage due to concentration of an electric field can be prevented. The insulating film pattern can be made smaller due to the insulating film layer being made more thin, and high integration is possible.
Further, after the upper electrode is formed, the resist pattern for forming the lower electrode is formed, and the insulating film layer and the first metal layer are subjected to etching processing. Namely, even if a pattern is not directly formed on the first metal layer, after a one-time process of forming a resist pattern for forming the lower electrode, the insulating film layer and the first metal layer are subjected to etching processing, such that the lower electrode and the wiring pattern can thereby be formed simultaneously. Accordingly, the number of processes can be reduced as compared to the number of processes in the conventional art.
In order to achieve the above-described object, a second aspect of the present invention is a method of fabricating a semiconductor device equipped with a capacitor portion, the method comprising the steps of: successively layering, on a substrate, a first metal layer which may become a lower electrode and a wiring pattern, a first insulating film layer, and a second metal layer which becomes an upper electrode; forming the upper electrode by subjecting the second metal layer to etching processing by using a resist pattern; layering a second insulating film layer on a surface of the substrate after the etching processing; forming, from above the second insulating film layer, a resist pattern for forming the lower electrode and the wiring pattern, at a region which covers the upper electrode; etching the first insulating film layer and the second insulating film layer in accordance with the resist pattern; and etching the first metal layer by using the first insulating film layer and the second insulating film layer as an etching mask.
In accordance with the second aspect, in addition to the operation and effects of the first aspect, the insulating film layer is formed on the entire surface after the upper electrode has been formed. At the time of forming the lower electrode and the wiring pattern, the first metal layer is subjected to etching processing by using the first insulating film layer and the second insulating film layer as an etching mask. Therefore, the aspect ratio at the time of etching the metal layer portions used as the wires can be reduced. Even if there are fine wires, stable working is possible, and high integration of the semiconductor device can be realized.
In order to achieve the above object, a third aspect of the present invention is a method of fabricating a semiconductor device equipped with a capacitor portion, the method comprising the steps of: successively layering, on a substrate, a first metal layer which may become a lower electrode and a wiring pattern, an insulating film layer, and a second metal layer which may become an upper electrode; forming, from above the second metal layer, a resist pattern for forming the lower electrode and the wiring pattern, at a region which covers a portion which may become the upper electrode; etching the second metal layer, the insulating film layer, and the first metal layer in accordance with the resist pattern; forming, on the second metal layer, a resist pattern for forming the upper electrode; and forming the upper electrode by etching the second metal layer in accordance with the resist pattern.
In accordance with the third aspect, first, the insulating film layer and the second metal layer which may become the upper electrode are formed. Thereafter, patterning is successively carried out such that the upper electrode, the lower electrode, and the like are formed. Thus, no steps are formed at the first metal layer or the second metal layer. No remains of metal wires are generated at the time of etching processing, and reliability is improved.
Further, because there are no corner portions at the insulating film layer between the upper electrode and the lower electrode, a lowering of breakdown voltage at end portions of the insulating film layer and a lowering of breakdown voltage caused by A deterioration of planarization can be prevented, and high integration is possible.
In order to achieve the above-described object, a fourth aspect of the present invention is a method of fabricating a semiconductor device equipped with a capacitor portion, the method comprising the steps of: layering, on a substrate, a first metal layer which may become a lower electrode and a wiring pattern; forming, on the first metal layer, a resist pattern for forming the lower electrode; etching the first metal layer in accordance with the resist pattern; layering a first insulating film layer on the first metal layer which has been subjected to etching; etching the first insulating film layer so as to leave portions, of the first insulating film layer, which are layered at openings between the lower electrode and the wiring pattern; layering a second insulating film layer and a second metal layer on the first metal layer which is exposed by the etching processing and on the first insulating film layer which is layered at the opening; and forming, on the second metal layer, a resist pattern for forming the upper electrode, and forming the upper electrode by etching the second metal layer in accordance with the resist pattern.
In accordance with the fourth aspect, the first insulating film layer is formed in advance at the opening between the lower electrode and the wiring pattern. Thus, thereafter, the second insulating film layer and the second metal layer are layered. No remains of the metal layer are generated at the time when the upper electrode and the like are formed, and reliability improves. Further, in the same way as in the third aspect, because there are no corner portions at the insulating film layer between the upper electrode and the lower electrode, a lowering of breakdown voltage at end portions of the insulating film layer and a lowering of breakdown voltage caused by a deterioration of planarization can be prevented, and high integration is possible.
In order to achieve the above-described object, a fifth aspect of the present invention is a method of fabricating a semiconductor device equipped with a capacitor portion, the method comprising the steps of: layering, on a substrate, a first metal layer which may become a lower electrode; oxidizing an upper layer portion of the first metal layer; layering a second metal layer, which may become an upper electrode, on the oxidized upper layer portion of the first metal layer; forming, from above the second metal layer, a resist pattern for forming the lower electrode and a wiring pattern, at a region which covers a portion which may become the upper electrode; etching the second metal layer and the first metal layer in accordance with the resist pattern; forming, on the second metal layer, a resist pattern for forming the upper electrode; and forming the upper electrode by etching the second metal layer in accordance with the resist pattern.
In accordance with the invention of the fifth aspect, there is no need to layer an insulating film layer on the lower electrode. Thus, the number of processes for fabricating the semiconductor device is reduced. Further, the first metal layer which may become the lower electrode and the second metal layer which may become the upper electrode are formed first, and thereafter, patterning is carried out successively, and the upper electrode, the lower electrode and the like are formed. Thus, no steps are formed at the first metal layer or the second metal layer. At the time of etching processing, no remains of the metal layers are generated, and reliability improves. Further, because there are no corner portions at the insulating film layer between the upper electrode and the lower electrode, a lowering of breakdown voltage at end portions of the insulating film layer and a lowering of breakdown voltage caused by a deterioration of planarization can be prevented, and high integration is possible.
Moreover, because the insulating film layer is formed by oxidation processing, a thinner insulating film layer can be formed precisely. Fabrication of a semiconductor device having a capacitor portion of an even greater capacity is possible.
In order to achieve the above-described object, a sixth aspect of the present invention is a method of fabricating a semiconductor device equipped with a capacitor portion, the method comprising the steps of: layering, on a substrate, a first metal layer which may become a lower electrode; nitriding an upper layer portion of the first metal layer; layering a second metal layer, which may become an upper electrode, on the nitrided upper layer portion of the first metal layer; forming, from above the second metal layer, a resist pattern for forming the lower electrode and a wiring pattern, at a region which covers a portion which may become the upper electrode; etching the second metal layer and the first metal layer in accordance with the resist pattern; forming, on the second metal layer, a resist pattern for forming the upper electrode; and forming the upper electrode by etching the second metal layer in accordance with the resist pattern.
In accordance with the sixth aspect, in addition to the operation and effects of the fifth aspect, due to the upper layer portion of the first metal layer being nitrided, the capacitor portion of the fabricated semiconductor device can have a greater capacity than in the case in which the upper layer portion of the first metal layer is oxidized.